Modern applications using analog-to-digital converters (ADCs) require an increasing amount of bandwidth. One way to achieve increased bandwidth without appreciable increase in power consumption is to utilize interleaved ADCs, i.e., two or more ADCs having a defined clocking relationship that are used to simultaneously sample an input signal and produce a combined output signal. The output signal of a set of interleaved ADCs results in a sampling bandwidth that is some multiple of the sampling bandwidths of the individual ADCs. Thus, the effective sampling rate can be increased by a factor that is equal to the number of ADCs implemented (e.g., using two ADCs each having a sample rate of fs will result in a sampling bandwidth of 2 fs).
Mismatch of the different interleaved channels can undesirably negate some of the benefits obtained by interleaving. For instance, time skew mismatch is a significant limiting factor when increased bandwidth is sought. Time skew mismatch occurs when the sampling intervals of the interleaved channels are unequal. Consider the case of a two-channel interleaved ADC. The interval between when channel 1 first samples an input signal and when channel 2 first samples the input signal should be equal to the interval between when channel 2 first samples the input signal and when channel 1 samples the input signal for the second time. If these intervals are not equal, a time skew mismatch exists on at least one of the channels. The difference between the two intervals is proportional to the amount of the time skew error.
Conventional time skew extraction techniques use a combination of multipliers and adders. This approach increases the amount of digital resources required, as well as the power consumption of the interleaved ADCs, particularly when dealing with a large number of interleaved channels. This approach also does not work at certain frequencies, and thus requires the use of notch filters to overcome this limitation.